1. Field of the Invention
The present invention generally relates to trap handlers architectures and more specifically to trap handler architectures in highly parallel thread processors and graphics processing units.
2. Description of the Related Art
Trap handlers are software routines in a computer system that are executed, for example, when an exception or interrupt occurs in the computer system during execution of a computer program. Exceptions occur as a result of executing a certain instruction in the computer program that causes an unexpected result that needs to be handled in a specific way. For example, an instruction to divide by zero or an instruction containing a bad memory address would generate an exception causing the flow of the computer program to jump into a trap handler routine. In contrast, interrupts occur due to external events that are not dependent upon the flow of computer program itself. For example, device I/O events such as a button press on a mouse or the completion of a data transfer to a NIC card will cause the device to transmit an interrupt to the computer system, similarly causing the flow of the computer program to jump into a trap handler routine. Whether dealing with exceptions or interrupts (collectively referred to herein as “exceptions”), a trap handler architecture typically begins by saving the state of the current computer program flow (e.g., onto the program stack) and then jumping into a particular subroutine in the trap handler to address the particular exception or interrupt.
Although trap handler architectures are commonly implemented in operating systems and device drivers of computer systems, to date, highly parallel thread processors such as graphics processing subsystems or GPUs (graphics processing units) in such computer systems have not incorporated trap handler architectures due difficulties in implementation and efficiency. Due to their highly parallelized nature, a trap handler architecture for a modern GPU needs to properly deal with tens of thousands of concurrently executing threads corresponding to multiple different thread groups that may be running within the GPU upon the occurrence of an interrupt or exception. Furthermore, integrated circuit components of such a trap handler architecture need to utilize semiconductor wafer die area efficiently given the size and cost constraints for GPUs. Due to the difficulties of incorporating a trap handler architecture that can efficiently deal with concurrently executing threads, current GPUs are not able to provide enhanced feature sets that are dependent on trap handlers, such as handling host CPU interrupts, exception handling directly within the GPU without interacting with the CPU, and GPU system call support.
Accordingly, what is needed in the art is a system and method for efficiently providing a trap handler architecture within an GPU that is able to properly handle the highly parallelized nature of currently running threads within the GPU.